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LT5546 40MHz to 500MHz VGA and I/Q Demodulator with 17MHz Baseband Bandwidth
FEATURES
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DESCRIPTIO
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17MHz I/Q Lowpass Output Noise Filters Wide Range 1.8V to 5.25V Supply Voltage Frequency Range: 40MHz to 500MHz THD < 0.14% (-57dBc) at 800mVP-P Differential Output Level IF Overload Detector Log Linear Gain Control Range: -7dB to 56dB Baseband I/Q Amplitude Imbalance: 0.2dB Baseband I/Q Phase Imbalance: 0.6 7.8dB Noise Figure at Max Gain Input IP3 at Low Gain: - 1dBm Low Supply Current: 24mA Low Delay Shift Over Gain Control Range: 2ps/dB Outputs Biased Up While in Standby 16-Lead QFN 4mm x 4mm Package with Exposed Pad
APPLICATIO S
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GPS IF Receivers Satellite IF Receivers VHF/UHF Receivers Wireless Local Loop
The LT(R)5546 is a 40MHz to 500MHz monolithic integrated quadrature demodulator with variable gain amplifier (VGA) and 17MHz I/Q baseband bandwidth designed for low voltage operation. It supports standards that use a linear modulation format. The chip consists of a VGA, quadrature downconverting mixers and 17MHz lowpass noise filters (LPF). The LO port consists of a divide-by-two stage and LO buffers. The IC provides all building blocks for IF downconversion to I and Q baseband signals with a single supply voltage of 1.8V to 5.25V. The VGA gain has a linearin-dB relationship to the control input voltage. Hard-clipping amplifiers at the mixer outputs reduce the recovery time from a signal overload condition. The lowpass filters reduce the out-of-band noise and spurious frequency components. The -3dB corner frequency of the noise filters is approximately 17MHz and has a first order rolloff. The standby mode provides reduced supply current and fast transient response into the normal operating mode when the I/Q outputs are AC-coupled to a baseband chip.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
280MHz IF INPUT L1 15nH C3 10pF L2 15nH IF +
C2 1F
C1 1nF VCC
1.8V
-25 -30 -35
IOUT+ IOUT-
IF
-
THD (dBc)
-40 -45 -50
GAIN CONTROL 2xLO C4 560MHz 3.3pF INPUT
VCTRL 2xLO + L3 39nH 2xLO - EN STBY GND /2
IF DET QOUT+ QOUT- LT5546
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C3 1.8pF
-55 -60 -60
C5 3.3pF
ENABLE STANDBY
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Total Harmonic Distortion vs IF Input Level at 1.8V Supply
fIF, 1 = 280MHz fIF, 2 = 280.1MHz f2xLO = 570MHz 800mVP-P DIFFERENTIAL OUT -40 -30 -20 -50 IF INPUT POWER EACH TONE (dBm) -10
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ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW QOUT+ QOUT- IOUT+ IOUT-
Supply Voltage ....................................................... 5.5V Differential Voltage Between 2xLO+ and 2xLO- .......... 4V IF+, IF- ............................................. -500mV to 500mV IOUT+, IOUT-, QOUT+, QOUT- .................. VCC - 1.8V to VCC Operating Ambient Temperature (Note 2) ...................................................-40C to 85C Storage Temperature Range ..................-65C to 125C Voltage on Any Pin Not to Exceed ........................ -500mV to VCC + 500mV
ORDER PART NUMBER
12 STBY
16 15 14 13 GND 1 IF+ 2 IF - 3 GND 4 5 VCC 6 VCTRL 7 IF DET 8 VCC 17
LT5546EUF
11 2xLO+ 10 2xLO- 9 EN
UF PART MARKING 5546
UF PACKAGE 16-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD IS GND (PIN 17) (MUST BE SOLDERED TO PCB)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
VCC = 3V, f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
SYMBOL IF Input fIF Frequency Range Nominal Input Level Input Impedance NF GL GH IIP3 IIP2 Noise Figure at Max Gain Min Gain (Note 4) Max Gain (Note 4) Input IP3, Min Gain Input IP3, Max Gain Input IP2, Min Gain Input IP2, Max Gain Nominal Voltage Swing Clipping Level DC Common Mode Voltage I/Q Amplitude Imbalance I/Q Phase Imbalance DC Offset Output Driving Capability ro Small-Signal Output Impedance STBY to Turn-On Delay I/Q Output 1dB Compression I/Q Output IM3 PIF, 1 = -25.5dBm, 280MHz PIF, 2 = -25.5dBm, 280.1MHz (Note 7) (Note 8) (Note 8) (Notes 6, 8) Single Ended, CLOAD 10pF (Note 6) 2 RSOURCE = 200 Differential IF+, IF- to GND, EN = VCC IF+, IF- to GND, EN = GND VCTRL = 1.7V VCTRL = 0.2V VCTRL = 1.7V PIF = -22.5dBm (Note 7) PIF = -75dBm (Note 7) VCTRL = 0.2V (Note 9) VCTRL = 1.7V (Note 9) (Note 6) (Note 6) 49 40 to 500 -76 to -19 100//1.2pF 1pF 7.8 1.6 56 -1 -49 36 -25 0.8 1.47 VCC - 1.19 0.14 0.6 21 1.5 180 0.3 -10 - 49 0.6 3 6 dB dB dB dBm dBm dBm dBm VP-P VP-P V dB Deg mV k s dBm dBc
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ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS MHz dBm
Demodulator I/Q Output
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LT5546
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Gain Slope Linearity Error Temperature Gain Shift Gain Control Response Time Gain Control Voltage Range Gain Control Slope Gain Control Input Impedance Delay Shift Over Gain Control Baseband Lowpass Filter (LPF) -3dB Cutoff Frequency Amplitude Roll-Off at 50MHz Group Delay Ripple 2xLO Input f2xLO P2xLO Frequency Range Input Power Input Power Input Impedance DC Common Mode Voltage IF Detector IF Detector Range Output Voltage Range Detector Response Time Power Supply VCC ICC IOFF ISTBY Mode Enable Disable Standby No Standby Enable Pin Voltage Enable Pin Voltage Standby Pin Voltage Standby Pin Voltage EN = High EN = Low STBY = High STBY = Low 1 0.5 1 0.5 V V V V Supply Voltage Supply Current Shutdown Current Standby Current EN = High, STBY = Low or High EN, STBY < 350mV EN = Low; STBY = High 1.8 24 0.2 3.6 5.25 34 30 6 V mA A mA Referred to IF Input For PIF = -30dBm to 8dBm With External 1.8pF Load, Settling within 10% of Final Value -30 to 8 0.27 to 1.2 80 dBm V ns 1:2 Transformer with 240 Shunt Resistor (Note 5) LC Balun (Note 5) Differential Between 2xLO+ and 2xLO- -20 80 to 1000 -5 -10 800//0.4pF VCC - 0.4 V MHz dBm dBm 13 17 -9 1 MHz dB ns To Internal 0.2V Reference Measured Over 10dB Step Variable Gain Amplifier (VGA) VCTRL = 0V to 1.4V T = -40C to 85C, VCTRL = 0V to 1.4V Settled within 10% of Final Value 0.5 0.4 90 0 to 1.7 41 25 2 dB dB ns V dB/V k ps/dB
VCC = 3V, f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Specifications over the -40C to 85C temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Tests are performed as shown in the configuration of Figure 6. The IF input transformer loss is substracted from the measured values. Note 4: Power gain is defined here as the I (or Q) output power into a 4k differential load, divided by the IF input power in dB. To calculate the voltage gain between the differential I output (or Q output) and the IF input, including ideal matching network, 10 * log(4k/50) = 19dB has to be added to this power gain.
Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2 transformer with 240 shunt resistor, 2xLO input power can be reduced to -10dBm, without degrading the phase imbalance. See Figure 11 and Figure 6. Note 6: Differential between IOUT+ and IOUT- (or differential between QOUT+ and QOUT-). Note 7: The gain control voltage VCTRL is set in such a way that the differential output voltage between IOUT+ and IOUT- (or differential between QOUT+ and QOUT-) is 800mVP-P, with the given input power PIF. IF frequencies are 280MHz and 280.1MHz, with f 2xLO = 570MHz. Note 8: The typical parameter is defined as the mean of the absolute values of the data distribution. Note 9: IF frequency is 125MHz, with f 2xLO = 502MHz.
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VCC = 3V, f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) Gain and Noise Figure Supply Current vs Supply Voltage vs Control Voltage at 3V Supply
28 85C
TYPICAL PERFOR A CE CHARACTERISTICS
SUPPLY CURRENT (mA)
26 25C 24 -40C 22
GAIN AND NOISE FIGURE (dB)
20 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V)
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Gain and Noise Figure vs Control Voltage at 1.8V Supply
60 GAIN DEVIATI0N FROM LINEAR FIT (dB) 50 GAIN AND NOISE FIGURE (dB) 40 30 20 NF 10 GAIN 0 -10 0 0.3 0.6 0.9 VCTRL (V)
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Gain and Noise Figure vs Control Voltage and VCC
60 50
GAIN AND NOISE FIGURE (dB)
60 50
GAIN AND NOISE FIGURE (dB)
40 30 20 NF 10 GAIN 0 -10 0 0.3 0.6 0.9 VCTRL (V)
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1.2 1.2
60 50 40 30 20 NF 10 GAIN 0 -10 0 0.3 0.6 0.9 VCTRL (V)
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fIF = 284MHz f2xLO = 570MHz 1.2 1.5 1.8
GAIN AT 25C NF AT 25C GAIN AT -40C NF AT -40C GAIN AT 85C NF AT 85C
Gain Flatness vs Control Voltage at 3V Supply
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.3 0.9 0.6 VCTRL (V) 1.2 1.5
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-40C
85C
fIF = 284MHz f2xLO = 570MHz 1.5 1.8
GAIN AT -40C NF AT 25C GAIN AT 25C NF AT -40C GAIN AT 85C NF AT 85C
25C
Gain and Noise Figure vs IF Frequency at 3V Supply
GAIN, VCTRL = 1.6V NF, VCTRL = 0.2V 40 GAIN, VCTRL = 0.9V 30 20 10 0 -10 10 100 IF FREQUENCY (MHz) 1000
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NF, VCTRL = 0.9V NF, VCTRL = 1.6V
fIF = 284MHz f2xLO = 570MHz 1.5 1.8
GAIN AT 1.8V NF AT 1.8V GAIN AT 3V NF AT 3V GAIN AT 5.25V NF AT 5.25V
GAIN, VCTRL = 0.2V
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VCC = 3V, f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) Total Harmonic Distortion vs IF Input Power at 3V Supply and 800mVP-P Differential Out
-25 -30 -35
THD (dBc) THD (dBc)
TYPICAL PERFOR A CE CHARACTERISTICS
Total Harmonic Distortion vs IF Input Power and IF Frequency
-25 -30 -35 -40 -45 -50 -55 -60 -60 fIF = 40MHz 800mVP-P DIFFERENTIAL OUT 3V SUPPLY
fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz
-40 25C -45 -40C -50 -55 -60 -60 85C
THD (dBc)
-20 -30 IF INPUT POWER EACH TONE (dBm)
-50
-40
Total Harmonic Distortion vs IF Input Power and Supply Voltage
800mVP-P DIFFERENTIAL OUT fIF,1 = 280MHz -30 f IF,2 = 280.1MHz f2xLO = 570MHz -35
THD (dBc)
-25
-35
MAGNITUDE (dB)
-40 -45 -50 1.8V -55 -60 -60 -50
THD (dBc)
3V
5.25V
-20 -30 IF INPUT POWER EACH TONE (dBm)
-40
LPF Frequency Response vs Baseband Frequency and Supply Voltage
0 -1 -2 MAGNITUDE (dB) -3 -4 -5 3V -6 -7 -8 -9 -10 0 5.25V
1.8V
IF DET OUTPUT (V)
IF DET OUTPUT (V)
5 10 15 20 25 30 35 40 45 50 55 BASEBAND FREQUENCY (MHz)
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Total Harmonic Distortion vs IF Input Power at 1.8V Supply and 800mVP-P Differential Out
-25 -30 -35 -40 -45 -50 fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz
25C -40C 85C
fIF = 280MHz -55 fIF = 500MHz -60 -60
-10
-20 -30 IF INPUT POWER EACH TONE (dBm)
-50
-40
-10
-50 -40 -20 -30 IF INPUT POWER EACH TONE (dBm)
-10
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Total Harmonic Distortion vs IF Input Power at 500mVP-P Differential Out
-20 -25 -30 fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz VCC = 3V 0 -1 -2 -40C -3 -4 -5
LPF Frequency Response vs Baseband Frequency and Temperature
VCC = 3V
-40C
-40 -45 -50 -55 -60 25C 85C
25C -6 -7 -8 -9 -10 85C
-10
-65 -40
-35 -30 -25 IF INPUT POWER EACH TONE (dBm)
-20
0
5 10 15 20 25 30 35 40 45 50 55 BASEBAND FREQUENCY (MHz)
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IF Detector Output Voltage vs IF Input CW Power at 3V Supply
1.4 1.2 1.0 85C 0.8 25C 0.6 0.4 fIF = 280MHz 1.4 1.2 1.0
IF Detector Output Voltage vs IF Input CW Power at 1.8V Supply
fIF = 280MHz
TA = 25C
85C 0.8 0.6 0.4 25C
-40C -30 -20 -10 0 IF INPUT CW POWER (dBm) 10
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-40C -30 -20 -10 0 IF INPUT CW POWER (dBm) 10
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0.2 -40
0.2 -40
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VCC = 3V, f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) IF Detector Output Voltage vs IF Input CW Power and Supply Voltage
1.4 1.2 fIF = 280MHz
1.4 1.2
TYPICAL PERFOR A CE CHARACTERISTICS
IF DET OUTPUT (V)
IF DET OUTPUT (V)
3V 1.8V
PHASE (DEG)
1.0 0.8 0.6 0.4 0.2 -40
5.25V
-30 -20 -10 0 IF INPUT CW POWER (dBm)
PI FU CTIO S
GND (Pins 1, 4 and 17): Ground. Pins 1 and 4 are connected to each other internally. The exposed pad (Pin 17) is not connected internally to Pins 1 and 4. For chip functionality, the exposed pad and either Pin 1 or Pin 4 must be connected to ground. For best RF performance, Pin 1, Pin 4 and the exposed pad should be connected to RF ground. IF+, IF- (Pins 2, 3): Differential Inputs for the IF Signal. Each pin must be DC grounded through an external inductor or RF transformer with central ground tap. This path should have a DC resistance lower than 2 to ground. VCC (Pins 5 and 8): Power Supply. These pins should be decoupled to ground using 1000pF and 0.1F capacitors. VCTRL (Pin 6): VGA Gain Control Input. This pin controls the IF gain and its typical input voltage range is 0.2V to 1.7V. It is internally biased via a 25k resistor to 0.2V, setting a low gain if the VCTRL pin is left floating. IF DET (Pin 7): IF Detector Output. For strong IF input signals, the DC level at this pin is a function of the IF input signal level. EN (Pin 9): Enable Input. When the enable pin voltage is higher than 1V, the IC is completely turned on. When the input voltage is less than 0.5V, the IC is turned off, except the part of the circuit associated with standby mode. 2xLO-, 2xLO+ (Pins 10, 11): Differential Inputs for the 2xLO Input. The 2xLO input frequency must be twice that of the IF frequency. The internal bias voltage is VCC - 0.4V. STBY (Pin 12): Standby Input. When the STBY pin is higher than 1V, the standby mode circuit is turned on to prebias the I/Q buffers. When the STBY pin is less than 0.5V, the standby mode circuit is turned off. QOUT-, QOUT+ (Pins 13, 14): Differential Baseband Outputs of the Q Channel. Internally biased at VCC - 1.19V. IOUT-, IOUT+ (Pins 15, 16): Differential Baseband Outputs of the I Channel. Internally biased at VCC - 1.19V.
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IF Detector Output Voltage vs IF Input CW Power and IF Frequency
VCC = 3V
Phase Relation Between I and Q Outputs vs LO Input Power
95 94 fIF = 284MHz, 25C fIF = 284MHz, -40C fIF = 284MHz, 85C fIF = 40MHz, 25C fIF = 500MHz, 25C
fIF = 500MHz fIF = 280MHz
1.0 0.8 0.6 0.4 0.2 -40 fIF = 40MHz
93 92 91 90 89 VCC = 3V 88 -20 -15
-30
0 IF INPUT CW POWER (dBm)
-20
-10
10
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0 -5 -10 LO INPUT POWER (dBm)
5
10
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VCC 5 IF + 2 IF - 3 VGA I-MIXER VCC 8 LPF CLIPPER 16 IOUT+ 15 IOUT- 7 IF DET VCTRL 6 2xLO + 11 /2 2xLO - 10 9 EN 1 4 17
DETECTOR
90
Q-MIXER LPF
+ 14 QOUT
0
CLIPPER 12 STBY
- 13 QOUT
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APPLICATIO S I FOR ATIO
The LT5546 consists of a variable gain amplifier (VGA), I/Q demodulator, quadrature LO generator, lowpass filters (LPFs), clipping amplifiers (clippers) and bias circuitry. The IF signal is fed to the inputs of the VGA. The VGA gain is typically set by an external signal in such a way that the amplified IF signal delivered to the I/Q mixers is constant. The IF signal is then converted into I/Q baseband signals using the I/Q down-converting mixers. The quadrature LO signals that drive the mixers are internally generated from the on-chip divide-by-two circuit. The I/Q signals are passed through first-order low-pass filters and subsequently a pair of hard-clipping amplifiers (clippers). After externally setting the required gain, these amplifiers should not clip. However, in the event of overload, they reduce the settling time of any (optional) external AC coupling capacitors by preventing asymmetrical charging and discharging effects. The I/Q baseband outputs are buffered by output drivers. VGA and Input Matching The VGA has a nominal 60dB gain control range with a frequency range of 40MHz to 500MHz. The inputs of the VGA must have a DC return to ground. This can be done using a transformer with a central tap (on the secondary) or an LC matching circuit with a matched impedance at the frequency of interest and near zero impedance at DC. The differential AC input impedance of the LT5546 is about 200, thus a 1:4 (impedance ratio) RF transformer with center tap can be used. In Figure 6, the evaluation board
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schematic is shown using a 1:4 transformer. The measured input sensitivity of this board is about -80.5dBm for a 10dB signal-to-noise ratio. In the case of an L-C matching circuit, the circuit of Figure 1 can be used. In Table 1 the matching network component values are given for a range of IF frequencies. The matching circuit of Figure 1 approaches 180 phase shift between IF+ and IF- in a broad range around its center frequency. However, some amplitude mismatch occurs if the circuit is not tuned to the center frequency. This leads to reduced circuit linearity performance, because one of the inputs carries a higher signal compared to the perfectly balanced case. A 10% frequency shift from the center frequency results in about a 2dB gain difference between the IF+ and IF- inputs. This results in a 1.5dB higher IM3 contribution from the input stage which leads to a 0.75dB drop in IIP3. Moreover, the IIP2 of the circuit is also reduced which can lead to a higher second order harmonic contribution. The circuit can be driven single ended, but this is not recommended because it leads to a 3dB drop in gain and a considerable increase in IM5 and IM7 components. The single-ended noise figure increases by 4dB if one IF input is directly grounded and increases by 1.5dB if one IF input is grounded via a 1H inductor. An IF input cannot be left open or connected via a resistor to ground because this will disturb the internal biasing, reducing the gain, noise and linearity performance. For optimal performance, it is important to keep the DC impedance to ground of both IF inputs lower than 2. In the matching network of Figure 1, inductor L3 is used for supplying the DC bias current to the IF+ input.
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APPLICATIO S I FOR ATIO
C3 56pF IF INPUT L1 56nH TO IF
+
TO IF - L3 120nH C1 5.6pF L2 56nH C2 5.6pF L1 15nH
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Figure 1. Example L-C IF Input Matching Network at 280MHz Table 1. The Component Values of Matching Network L1, L2, L3, C1, C2 and C3.
fIF(MHz) 50 100 150 200 250 300 350 400 450 500 L1, L2(nH) 340 159 106 80 64 53 45 40 35 32 C1, C2(pF) 34 15.9 10.6 8.0 6.4 5.3 4.5 4.0 3.5 3.2 L3(nH) 1800 470 470 470 120 120 120 120 120 120 C3(pF) 820 220 220 220 56 56 56 56 56 56
To keep the DC resistance of L3 below 2, 120nH is used. This disturbs the matching network slightly by causing the frequency where the S11 is minimal to be lower than the frequency where the amplitudes of IF+ and IF- are equal. To compensate for this, the value of coupling capacitor C3 is lowered and will contribute some correcting reactance. For low frequencies, it might not be possible to find any practical inductor value for L3 with DC resistance smaller than 2. In that case it is recommended to use a transformer with a center tap. The tolerance for the components in Figure 1 can be 10% for a return loss higher than 16dB and a gain reduction due to mismatch less than 0.3dB. It is possible to simplify the input matching circuit and compromise the performance. In Figure 2a, the simplified matching network is given. This matching network can deliver equal amplitudes to the IF + and IF - inputs for a narrow frequency region, but the phase difference between the inputs will not be exactly 180 degrees. In practice, the phase shift will be around 145
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IF INPUT TO IF + C1 10pF TO IF - L2 15nH 75 1mA VBIAS 1mA 75 IF + IF -
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(2a)
(2b)
Figure 2a. Simplified IF Input Matching Network at 280MHz and Figure 2b. Simplified Circuit Schematic of the IF Inputs
degrees, depending on the quality factor of the network. This will result in a reduction in the gain. The higher the chosen quality factor, the closer the phase difference will approach 180 degrees. However, a higher quality factor will reduce bandwidth and create more loss in the matching network. For minimum board space, 0402 components are used. The measured noise figure for maximum gain with this matching network is about 9.4dB, and the maximum gain is about 55dB. Assuming 0402 inductors with Q = 35, the insertion loss of this network is about 2.5dB. The tolerance for the components in Figure 2a can be 10% for a return loss higher than 10dB and a gain reduction due to mismatch less than 0.5dB. The measured input sensitivity for this matching network (see also Figure 11) is about -78.3dBm for a 10dB signal-to-noise ratio. The gain of the VGA is set by the voltage at the VCTRL pin. For high gain settings, both the noise figure and the input IP3 will be low. From a noise figure point of view, it is advantageous to work as closely as possible to the maximum gain point. However, if the voltage at the VCTRL pin is increased beyond the maximum gain point (where additional increase in control voltage does not give an increase in gain), the response time of the gain control circuit is increased. If control speed is crucial, a few dB of gain margin should be allowed from the highest gain point to be sure that at all temperatures, the maximum gain setting is not crossed. At low gain settings, the noise figure and the input IP3 will be high. Optionally, the control voltage VCTRL can be set lower than 0.2V. The normal range is from VCTRL = 0.2V to 1.7V, which results in a nominal gain range from 1.6dB to 56.8dB. The linear-indB gain relation with the VCTRL voltage still holds for control voltages as low as -0.35V. This results in an
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APPLICATIO S I FOR ATIO
extended gain control range of -23dB to 57dB. The VCTRL pin is a very sensitive input because of its high input impedance and therefore should be well shielded. Signal pickup on the VCTRL pin can lead to spurs and increased noise floor in the I/Q baseband outputs. It can degrade the linearity performance and it can cause asymmetry in the two-tone test. If control speed is not important, 1F bypass capacitors are recommended between VCTRL and ground. A fast responding peak detector is connected to the VGA input, sensitive to signal levels above the signal levels where the VGA is operating in the linear range. It is active from -22dBm up to 5dBm IF input signal levels. The DC output voltage of this detector (IF DET) can be used by the baseband controller to quickly determine the presence of a strong input level at the desired channel, and adjust gain accordingly. Figure 3a shows the simplified circuit schematic of the IF DET output. I/Q Demodulators The quadrature demodulators are double balanced mixers, down-converting the amplified IF signal from the VGA into I/Q baseband signals. The quadrature LO signals are generated internally from a double frequency external CW signal. The nominal output voltage of the differential I/Q baseband signals should be set to 0.8VP-P or lower, depending on the linearity requirements. The magnitudes of I and Q are well matched and their phases are 90 apart. Quadrature LO Generator The quadrature LO generator consists of a divide-by-two circuit and LO buffers. An input signal (2xLO) with twice the desired IF signal frequency is used as the clock for the divide-by-two circuit, producing the quadrature LO signals for the demodulators. The outputs are buffered and then drive the down-converting mixers. With a fully differential approach, the quadrature LO signals are well matched. Second harmonic content (or higher order even harmonics) in the external 2xLO signal can degrade the 90 phase shift between I and Q. Therefore, such content should be minimized. In disable or standby mode, the divide-by-two stage is powered down. After enabling the circuit, the phase relation between the IF signal and the baseband (I or Q) signals can be either 0 or 180, since the circuit cannot distinguish between the two subsequent identical sinusoi-
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VCC VCC + 400mV - 8k 8k 2xLO + 2xLO - IF DET 1k 3.8k
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(3a)
(3b)
Figure 3a. Simplified Circuit Schematic of the IF DET Output and Figure 3b. The 2xLO Inputs
3.3pF 2xLO INPUT 39nH TO 2xLO- 3.3pF TO 2xLO-
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100pF TO 2xLO+ 1:4 2xLO INPUT 2xLO INPUT 56 TO 2xLO+ 240 TO 2xLO- 100pF TO 2xLO+
(4a)
(4b)
(4c)
Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band Tuned to 570MHz, 4b) Wide Band, 4c) Single-Ended Wide Band
dal waveforms of the 2xLO input signal. The phase relation between I and Q is always 90, i.e. I always leads Q by 90. Figure 3b shows the simplified circuit schematic of the 2xLO inputs. Depending on the application, different 2xLO input matching networks can be chosen. In Figure 4, three examples are given. The first network provides the best 2xLO input sensitivity because it can boost the 2xLO differential input signal using a narrow-band resonant approach. The second network gives a wide-band match, but the 2xLO input sensitivity is about 2dB lower. The third network gives a simple and less expensive wide-band match, but 2xLO input sensitivity drops by about 9dB. The IF input sensitivity doesn't change significantly using any of the three 2xLO matching networks. Baseband Circuit The baseband circuit consists of I/Q low-pass filters, I/Q hard limiters (clippers) and I/Q output buffers. The hard limiters operate as linear amplifiers normally. However, if a high level input temporarily overloads a linear amplifier, then the circuit will limit symmetrically, which will help to prevent the output buffer from overloading. This speeds
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LT5546
APPLICATIO S I FOR ATIO
up recovery from an overload event, which can occur during the gain settling. The clipping level is approximately constant over temperature. The first order integrated lowpass filters are used for noise filtering of the down-converted baseband signals for both the I channel and the Q channel. These filters are well matched in gain response. The -3dB corner frequency is typically 17MHz. The I/Q outputs can drive 2k in parallel with a maximum capacitive loading of 10pF at 5MHz, from all four pins to ground. The outputs are internally biased at VCC - 1.19V. Figure 5 shows the simplified output circuit schematic of the I channel or Q channel. The I/Q baseband outputs can be DC-coupled to the inputs of a baseband chip. For AC-coupled applications with large capacitors, the STBY pin can be used to pre-bias the outputs to nominal VCC - 1.19V at much reduced current. This mode draws only 3.6mA supply current. When the EN pin is then driven high (>1V), the chip is quickly switched to normal operating mode, avoiding the introduction of large charging time constants. Table 2 shows the logic of the EN pin and STBY pin. In both normal operating mode
OPTIONAL VCC3 C37 0.1F R50 2k C35 4.7F C34 R45 0.1F 1k C1 5.6pF R46 3.09k R49 2k C32 1pF 16 15 C33 0.1F
J1 IOUT
R47 49.9
C31 1F 6
7
+ -
3
U3 LT1818CS 4
2
R48 3.09k
J3 IFIN
C43 22nF
T1, 1:4,TR-R JTX-4-10T MINI-CIRCUITS 1 6
1 2 3 4
VCC1 C22 1F VCTRL R51 100 C25 1.5pF C16 1nF C15 1nF SW1 OVERLOAD C26 NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED 1.8pF COMPONENTS ARE INCLUDED FOR EVALUATION ONLY. DEMO BOARD: DC696A C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL C39 1F
5546 F04
Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers
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and standby mode, the maximum discharging current is about 300A, and the maximum charging current is more than 4mA. In Figure 5 the simplified circuit schematic of the STBY (or EN) input is shown.
Table 2. The Logic of Different Operating Modes
EN Low Low High STBY Low High Low or High Comments Shutdown Mode Standby Mode Normal Operation Mode
VCC VCC I CHANNEL (OR Q CHANNEL): DIFFERENTIAL SIGNALS FROM LPF IOUT+ (OR QOUT+) IOUT- (OR QOUT-) STBY (OR EN) 300A 300A
5546 F05
W
UU
22k
Figure 5. Simplified Circuit Schematic of I Channel (or Q Channel) Outputs and STBY (or EN) Input
IOUT+ IOUT- QOUT+ QOUT- C36 4.7F C27 0.1F R41 1k R39 3.09k C28 0.1F R42 2k C29 1pF 14 13 VCC2 IOUT+ IOUT- QOUT+ QOUT- GND IF + IF - GND U1 LT5546 12 11 R52 240 6 1 R36 20k IF VCC VCTRL DET VCC 5 6 7 8 17 GND 1 = EN 2 = STBY T2, 1:4, TR-R C45 22nF JTX-4-10T MINI-CIRCUITS J4 2XLO R35 20k C2 5.6pF 5V C38 0.1F
R43 2k
3
+ -
7 6
C30 1F
2
U2 LT1818CS 4
R44 49.9
J2 QOUT
R40 3.09k
STBY 2XLO+
10 2XLO - EN 9
LT5546
APPLICATIO S I FOR ATIO
Evaluation Board
The evaluation circuit schematic is drawn in Figure 6. The components associated with buffers U2 and U3 are included to drive a 50 load for evaluation purposes only.
Figure 7. Component Side Silkscreen of Evaluation Board
Figure 9. Bottom Side Silkscreen of Evaluation Board
15nH RX INPUT: 2.4GHz TO 2.5GHz 1.8V 1F 2 VGA 15nH 3 0 7 6 Q-MIXER 90 f/2 12 LT5546 3.3pF 1,4,17 9 STBY EN
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10pF 280MHz IF SAW BP FILTER
RX FRONT END 1ST LO, 2.12GHz TO 2.22GHz MAIN SYNTHESIZER 2ND LO, 560MHz -10dBm 3.3pF
AUX SYNTHESIZER
11 39nH 10
Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
There is a unity voltage gain relationship for AC signals between the evaluation board outputs (I and Q) and the IOUT+, IOUT- or QOUT+ and QOUT- outputs of the LT5546 when the evaluation board outputs are terminated in 50.
Figure 8. Component Side Layout of Evaluation Board Figure 10. Bottom Side Layout of Evaluation Board
1nF VCC 5, 8 I-MIXER LPF HARD CLIPPER 16 15 I-OUTPUTS IF DET VCTRL Q-OUTPUTS BASEBAND PROCESSOR A/D A/D D/A A/D 14 13 LPF HARD CLIPPER
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UU
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LT5546
PACKAGE DESCRIPTIO
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (4 SIDES) 0.72 0.05 PIN 1 TOP MARK 0.75 0.05
4.35 0.05 2.15 0.05 2.90 0.05 (4 SIDES)
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. ALL DIMENSIONS ARE IN MILLIMETERS
0.30 0.05 0.65 BCS
RELATED PARTS
PART NUMBER Infrastructure LT5511 LT5512 LT5515 DESCRIPTION COMMENTS RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer DC-3GHz, 20dBm IIP3, Integrated LO Buffer 20dBm IIP3, NF =16.8dB, Integrated LO Quadrature Generator 4V to 5.25V Supply, 21.5dBm IIP3, NF = 12.8dB, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports 2.7V to 5.25V Supply, 80dB Dynamic Range, Temperature Compensated 2.7V to 6V Supply, 300MHz to 3.5GHz, Temperature Compensated 2.7V to 6V Supply, 48dB Dynamic Range, Temperature Compensated 2.7V to 6V Supply, 44dB Dynamic Range, Temperature Compensated -30dBm to 6dBm, 600A Supply Current, Temperature Compensated Precision VOUT Offset Control, Adjustable Gain and Offset 1.8V to 5.25V Supply, Dual-Gain LNA, Mixer 1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain, 90dB RSSI Range 1.8V to 5.25V Supply, Four Step RF Power Control, 120MHz Modulation Bandwidth 1.8V to 5.25V, I/Q Baseband Bandwidth 8.8MHz, -40dB to 57dB Linear Power Gain High Signal Level Upconverting Mixer High Signal Level Downconverting Mixer 1.5GHz to 2.5GHz Direct-Conversion Quadrature Demodulator LT5516 800MHz to 1.5GHz Direct-Conversion Quadrature Demodulator LT5522 600MHz to 2.7GHz High Signal Level Downconverting Mixer RF Power Detectors LT5504 800MHz to 2.7GHz RF Measuring Receiver LTC5505 RF Power Detectors with >40dB Dynamic Range LTC5507 100kHz to 1000MHz RF Power Detector LTC5508 0.3GHz to 7GHz RF Power Detector LTC5509 300MHz to 3GHz RF Power Detector LTC5532 300MHz to 7GHz Precision RF Power Detector RF Receiver Building Blocks LT5500 1.8GHz to 2.7GHz Receiver Front End LT5502 400MHz Quadrature IF Demodulator with RSSI LT5503 1.2GHz to 2.7GHz Direct IQ Modulator and Mixer LT5506 40MHz to 500MHz Quadrature IF Demodulator with VGA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
UF Package 16-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1692)
BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 0.55 0.20 15 16 1 2.15 0.10 (4-SIDES) 2 PACKAGE OUTLINE 0.200 REF 0.00 - 0.05
(UF) QFN 0802
0.30 0.05 0.65 BSC
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED
5546f LT/TP 1003 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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